DRAMs generally use a large number of memory cell capacitors in storing data. The data stored in each memory cell capacitor is typically accessed through a metal-oxide semiconductor field effect transistor (MOSFET). However, because a significant amount of charge will leak from the memory cell capacitors in typical conventional DRAM designs, the leakage of a memory capacitor in DRAM designs is a major issue. As is well known, DRAMs use memory refresh cycles to compensate for the capacitor leakage so as to retain data in the memory cells. However, memory refresh cycles consume power and time. To reduce refresh power or refresh rate, it is essential to reduce leakage of the memory capacitor.
Two major causes of the memory cell capacitor leakage are junction leakage and channel leakage caused by wordline disturbances. Junction leakage is the result of the reverse saturation current of the access transistor of the memory cell, which leaks to the substrate. As is well known, the reverse saturation current of a MOSFET is strongly dependent on process parameters.
On the other hand, the channel leakage caused by wordline disturbances results when noise from a noise source (e.g., switching noise on nearby wordline) is coupled to the wordline. Because the wordline is typically connected to the gate of the access transistor, the coupled noise may cause the access transistor to become momentarily conductive. Consequently, charge stored in the cell capacitor may leak if the capacitor is charged (e.g., storing a high voltage), or charge may enter the capacitor from the bitline if the capacitor is discharged (e.g., storing a low voltage).
In FIG. 1, a typical DRAM memory cell 8 consists of a storage capacitor 10 and an access transistor 12. Although the conventional DRAM memory cell 8 is well known, the following description is provided for completeness. The access transistor 12 is typically a n-channel MOSFET, with one source/drain (S/D) node 11 being connected to a node 17 of the capacitor 10. The node 17 is referred to herein as the storage node. The other S/D node 13 of the access transistor 12 is connected to a bitline 14. The gate 15 of the access transistor 12 is connected to a word line 16. The other node 18 of the capacitor 10 is connected to a cell plate (not shown), which has impressed thereon a reference voltage Vcp.
In order to reduce leakage caused by wordline disturbance, a high threshold-voltage (Vt) access transistor can be used to reduce subthreshold current. However, this type of transistor is relatively slow, making its use as an access transistor undesirable. Another conventional method impresses a negative bias on the wordline when the wordline is not being accessed. More specifically, a negative voltage is applied to the wordline 16 to reverse bias the gate-to-source junction of the access transistor 12, thereby preventing the access transistor from conducting. This scheme is described in more detail in conjunction with the timing diagram of FIG. 2.
With reference to FIGS. 1 and 2 the negative bias wordline scheme is performed as follows. During a time period T1, the DRAM cell is in the active mode, being accessed in either the access mode or the refresh mode. During the active mode, a positive voltage is impressed on the word line 14, thereby causing the access transistor 12 to become conductive. Typically, this positive wordline voltage is greater than the NMOS "drain" voltage VDD provided by a VDD voltage source (not shown). Then, depending on the voltage on the bitline 14, the capacitor 10 is either charged to a voltage approximately equal to VDD or discharged to a voltage approximately equal to the NMOS "source" voltage VSS. In this conventional scheme, the cell plate voltage Vcp is typically maintained at a value of 1/2VDD for all operations. Thus, the voltage across the capacitor 10 is about +1/2VDD when storing a high voltage and about zero when storing a low voltage.
Then during a time period T2, the DRAM cell is not accessed. A negative voltage is impressed on the wordline 16. Because the gate 15 is connected to the wordline 16, the resulting negative gate voltage provides a large noise margin, thereby reducing leakage caused by wordline disturbance.
One disadvantage of this scheme is that extra control circuitry is required to provide the negative voltage to each of the wordlines. Because DRAM devices typically have a large number of wordlines, a significant amount of area is needed to provide this extra control circuitry. In addition, a relatively large amount of power is dissipated to pull the wordlines to below Vss. Moreover, because the backbias voltage generator is typically used to provide the negative voltage to cell plate, discharging the wordlines undesirably introduces a significant amount of noise into the backbias voltage -Vbb and disturbs memory cells through cell plate.
A further problem arises in the presence of a bitline-to-wordline short (cross-fail), which causes the memory cells connected to the shorted wordline or bitline to malfunction. A cross-fail may exist in a DRAM because redundancy circuits are often used to replace memory cells affected by cross-fail.
The cross-fail increases the power dissipation of the DRAM as current is conducted from the precharge circuit (not shown), the shorted bitline, the shorted wordline and the wordline pulldown transistor. The cross-fail increases more leakage because the wordlines are pulled down to the backbias voltage -Vbb instead of ground. This causes the gate-to-source voltage of the pull-down transistor to increase, resulting high stand by current of the device. To reduce leakage current to a reasonable level, the width of the wordline pull-down transistor is typically reduced to the minimum device size. A long channel pulldown transistor may be necessary to reduce the leakage to a tolerable level. But the weaker pull-down transistor causes pull-down operation to become slower.
Alternatively, cross-fail leakage may be reduced by using a pulsed precharge scheme. In this scheme, the bitlines are precharged to the predefined voltage level for a limited duration before the memory access. Although this scheme reduces the cross-fail leakage, the bitline is undesirably left floating when there is no memory access.